As modern CMOS technology is scaled down, the effects of die-to-die and within-die variations are becoming worse. Process variations can be categorized into four tiers, lot-to-lot variations, wafer-to-wafer variations, die-to-die variations, and within-die variations. For high performance VLSI chips, die-to-die and within-die variations have a significant impact on their performance and power consumption. Even though significant advances have been made to reduce process variations, silicon manufacturers have not been able to keep up with technology scaling. An existing statistical model, assuming a 3σ channel length deviation of 20% for the 50-nm technology generations, indicates that essentially a generation of performance gain can be lost due to systematic within-die variations.
Small variations in spatial dimensions are becoming large relative to the critical dimensions in manufacturing processes. These large relative variations cause wide distributions of circuit operating frequencies and power dissipation. The distributions in frequency and power determine the percentage of circuits or chips, that meet both a minimum frequency, ft, and the power dissipation constraint, Pt. Given a fixed set of constraints, wider distributions make for lower binning yields after production.
Attempts have been made to adjust n-channel field effect transistor (nfet) and p-channel field effect transistor (pfet) body biases to affect the operating frequency and power consumption, thus, to improve product binning. Researchers beginning in 1995 have discussed the use of adaptive body bias (ABB) to reduce the transistor threshold voltage to retain device performance.
Recent work described an adaptive biasing method using an on-chip measuring circuit to determine the required back bias. Results suggest that, while the simplest implementation of ABB was effective in mitigating the effects of die-to-die (D2D) variation, its effect on within-die (WD) variation was limited. For this approach to be truly effective, Vnb (the body voltage of the nfets) needs to be adjusted separately for each section of the circuit, which dictates using a triple-well process to generate both n-wells and p-wells. The effectiveness of this method is further limited by the size of the sections used. Increasing the effectiveness requires adding another power grid section, along with a replica critical path, phase detector, counter, and R-2R ladder digital-to-analog (D/A) converter. This proves to be enormously expensive in both die area and routing resources. Also, localized areas of high variations within a section are not addressed.